View WM2152_348327.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

w
12-bit, 30MSPS ADC
DESCRIPTION
The WM2152 is a high speed 12-bit analog-to-digital converter operating on a 3.3V supply. This device includes a high bandwidth sample and hold and internal voltage references. Conversion is controlled by a single clock input. The device has a differential sample and hold input which gives excellent common-mode noise immunity and low distortion. The maximum differential input voltage can be set by the user, via two mode selection pins, to be 1V or 2V. A third PGA mode is designed particularly for single-ended input signals such as composite video sources. Singleended input signals require one side of the differential input to be tied to an external voltage source. The device provides internal reference voltages for setting the ADC full-scale range without the requirement for external circuitry. The WM2152 can also accept external reference levels for applications where common or high precision references are required. The WM2152 provides an out of range indicator flag to indicate when the input signal exceeds the converter's full scale range. An output enable pin allows several devices to share a common bus. Power down mode for the device is under the control of the two mode control pins and takes power consumption down to less than 36W.
WM2152
FEATURES
* * * * * * * * * 12-bit resolution ADC 30MSPS conversion rate Programmable Gain Amplifier (PGA) Out of range indicator Low power - 168mW typical at 3.3V supplies Powerdown mode to < 36W 66dB SNR for 3.58MHz input signal -78db THD for 3.58MHz input signal 28-pin TSSOP package
APPLICATIONS
* * * * * * Direct IF sampling Baseband digitisation Video Digitisation Portable instrumentation Digital imaging High speed data acquisition
BLOCK DIAGRAM
AVDD1 AGND1 AVDD2 AGND2
CON0 CON1
CONFIGURATION CONTROL CIRCUIT
INTERNAL CLOCKS
CLK
VINP
D[11:0]
VINM
+ PGA -
ADC
OUTPUT BUFFERS
OVRNG OEB
DVDD PRECISION REFERENCE CIRCUITS EXTREF VRT VRB DGND
WM2152
WOLFSON MICROELECTRONICS LTD
www.wolfsonmicro.com
Product Preview, August 2001, Rev 1.2
Copyright 2001 Wolfson Microelectronics Ltd.
WM2152 PIN CONFIGURATION
AGND2 CON1 CON0 EXTREF VINP VINM AGND1 AVDD1 VRT VRB OVRNG D11 D10 D9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 CLK AVDD2 OEB D0 D1 D2 D3 D4 DVDD DGND D5 D6 D7 D8
Product Preview
ORDERING INFORMATION
DEVICE XWM2152CDT/V XWM2152IDT/V TEMP. RANGE 0 to +70oC -40 to +85oC PACKAGE 28-pin TSSOP 28-pin TSSOP
PIN DESCRIPTION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 NAME AGND2 CON1 CON0 EXTREF VINP VINM AGND1 AVDD1 VRT VRB OVRNG D11 D10 D9 D8 D7 D6 D5 DGND DVDD D4 D3 D2 D1 D0 OEB AVDD2 CLK TYPE Supply Analog Input Analog Input Analog Input Analog Input Analog Input Supply Supply Analog I/O Analog I/O Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Digital Output Supply Supply Digital Output Digital Output Digital Output Digital Output Digital Output Digital Input Supply Analog Input Mode control pin 1 Mode control pin 0 Reference select pin (low = internal, high = external) Positive analog input Negative analog input Analog ground Analog power supply Upper ADC reference voltage (decoupling or external input) Lower ADC reference voltage (decoupling or external input) Out of range indicator (high = out-of-range) Data output bit 11 (MSB) Data output bit 10 Data output bit 9 Data output bit 8 Data output bit 7 Data output bit 6 Data output bit 5 Digital ground (digital input/output buffers only) Digital power supply (digital input/output buffers only) Data output bit 4 Data output bit 3 Data output bit 2 Data output bit 1 Data output bit 0 (LSB) Output enable (low = enable, high = disable) Analog Power Supply (for Internal Clocks) ADC conversion clock DESCRIPTION Analog Ground (for Internal Clocks)
w
PP Rev 1.2 August 2001 2
WM2152 ABSOLUTE MAXIMUM RATINGS
Product Preview
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. As per specifications IPC/JEDEC J-STD-020A and JEDEC A113-B, this product requires specific storage conditions prior to surface mount assembly. It has been classified as having a Moisture Sensitivity Level of 2 and as such will be supplied in vacuum-sealed moisture barrier bags. CONDITION Digital supply voltage, DVDD to DGND Internal clock supply voltage, AVDD2 to AGND2 Analog supply voltage, AVDD1 to AGND1 Maximum ground difference between AGND1, AGND2, and DGND Voltage range digital input (OEB) Voltage range analog inputs Voltage range CLK input Operating junction temperature range, TJ Storage temperature Lead temperature (1.6mm from package body for 10 seconds) Package Body Temperature (soldering 10 seconds) Package Body Temperature (soldering 2 minutes) MIN -0.3V -0.3V -0.3V -0.3V DGND - 0.3V AGND1 - 0.3V AGND1 - 0.3V -40C -65C MAX +4.0V +4.0V +4.0V +0.3V DVDD + 0.3V AVDD1 + 0.3V AVDD1 + 0.3V +150C +150C +300C +240C +183C
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range Analog supply range Ground Clock frequency Clock duty cycle Operating Free Air Temperature TA WM2152C WM2152I SYMBOL DVDD AVDD1, AVDD2 DGND, AGND1, AGND2 fCLK 45 0 -40 50 TEST CONDITIONS MIN 3.0 3.0 NOM 3.3 3.3 0 30 55 70 85 MAX 3.6 3.6 UNIT V V V MHz % C C
w
PP Rev 1.2 August 2001 3
WM2152 ELECTRICAL CHARACTERISTICS
Product Preview
Test Conditions: AVDD1 = AVDD2 = DVDD = 3.3V, fCLK = 30MHz, EXTREF = AGND, Mode=1, TA = TMIN to TMAX, unless otherwise stated. PARAMETER DC Characteristics Resolution Integral Nonlinearity Differential Nonlinearity Missing Codes Offset Error Gain Error Power supply rejection ratio Dynamic Performance (Note 1) Effective number of bits ENOB fIN =3.58MHz fIN =10MHz fIN =15MHz Total harmonic distortion THD fIN =3.58MHz fIN =10MHz fIN =15MHz SNR fIN =3.58MHz fIN =10MHz fIN =15MHz Signal to noise and distortion ratio Spurious free dynamic range SINAD fIN =3.58MHz fIN =10MHz fIN =15MHz SFDR fIN =3.58MHz fIN =10MHz fIN =15MHz Differential phase Differential gain Analog Input Signal to (VINP, VINM) Input Span, (VINP - VINM) Mode=1, VREF = 1V Mode=2, VREF = 1V Mode=3, VREF = 1V Input (VINP or VINM) range Input capacitance Analog input bandwidth Conversion Characteristics Conversion frequency Pipeline delay Aperture delay Aperture jitter Internal Voltage References (Note 3) Upper reference voltage Lower reference voltage Differential reference voltage (VRT-VRB) Power up time of references from standby Externally applied VRT reference range VRT VRB VREF tPU 0.95 2.15 1.15 1 100 1.05 V V V s tAD fCLK 5 5 2.0 2.0 30 MHz cycles of CLK ns ps rms CIN All modes All modes -1 -2 0 0 6 180 1 2 1 AVDD V V V V pF MHz DP DG 67 65.6 66 10.6 10.9 10.9 10.8 -76 -74 -72.5 68 68 67.7 67.4 67.4 66.6 78.1 76.4 74.6 0.12 0.01 -65 bits bits bits dB dB dB dB dB dB dB dB dB dB dB dB deg % PSRR INL DNL All modes All modes All modes All modes All modes 12 -2.5 1.2 0.4 0.5 0.5 54 +2 1 1.2 3.5 bits LSB LSB %FSR %FSR dB SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
No missing codes guaranteed
External Voltage References (EXTREF = AVDD1) 2 2.5 V
w
PP Rev 1.2 August 2001 4
WM2152
Product Preview
Test Conditions: AVDD1 = AVDD2 = DVDD = 3.3V, fCLK = 30MHz, EXTREF = AGND, Mode=1, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Externally applied VRB reference range Externally applied differential reference range (VRT-VRB) Reference Input Resistance (VRT to VRB) Digital Inputs / Outputs Input LOW level Input HIGH level Input current High level output voltage Low level output voltage High Impedance Output Current Rise/Fall time Input LOW level Input HIGH level Input current Power Supplies AVDD2 supply current AVDD1 supply current DVDD supply current Total supply current Total supply current in standby mode Power consumption Notes 1. 2. 3. Input amplitudes for all single tone dynamic tests are all -0.5dBFS. Inputs for two-tone IMD are 4.4MHz and 4.5MHz, each at -7dBFS. The internal reference voltage is not intended for use driving off-chip. IAA2 IAA1 IDD ITOT ISB fCLK = 0MHz 168 3.0 3.3 35 13 48 66 10 220 3.6 mA mA mA mA A mW VIL VIH 0.8 x AVDD1 +/- 1 CLOAD=10pF 5.5 0.2 x AVDD1 Analog Control Inputs (EXTREF, CON1, CON2), Clock Input (CLK) V V uA VOL VOH IOH=50A IOL=-50A DVDD-0.4 0.4 1 VIL VIH 0.8 x DVDD +/- 1 0.2 x DVDD V V uA V V A ns SYMBOL TEST CONDITIONS MIN 1.05 0.75 9 TYP MAX 1.3 1.05 UNIT V V k
w
PP Rev 1.2 August 2001 5
WM2152
Product Preview
Sample 2 Sample 1 Analogue Input at VINP, VINM
Sample 3 Sample 4
tCLK tAD
Sample 5
tCH tCL
Sample 6
Sample 7
CLK
tPD 5 x tCLK
Sample 1 Sample 2 Sample 3
Digital Output D[[11:0]
Figure 1. Input and output timing
OEB
tDEN
Digital Output D[[11:0] Hi-Z Data Data Data
tDZ
Data Hi-Z
Figure 2. Output enable timing Test Conditions: AVDD1 = AVDD2 = DVDD = 3.3V, fCLK = 30MHz, EXTREF = AGND, Mode=1, TA = TMIN to TMAX, unless otherwise stated. PARAMETER Timing Clock period Clock low or high Pipeline delay Clock to data valid Output disable to hi-Z output Output enable to data valid tPD tDZ tDEN 3.2 16 19 tCLK tCH, tCL 33.3 15 16.6 5 19 ns ns CLK cycles ns ns ns SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
w
PP Rev 1.2 August 2001 6
WM2152 TYPICAL SYSTEM PERFORMANCE
1
AVDD = DVDD = 3.3V, fS = 30MSPS
Product Preview
0.75 Differential Non-Linearity (LSBs) 0.5 0.25 0 -0.25 -0.5 -0.75 -1 0 512 1024 1536 2048 DIGITAL CODE 2560 3072 3584 4096
Figure 3 Differential Non-Linearity
1
AVDD = DVDD = 3.3V, fS = 30MSPS
0.75
Integral Non-Linearity (LSBs)
0.5
0.25
0
-0.25
-0.5
-0.75
-1 0 512 1024 1536 2048 DIGITAL CODE 2560 3072 3584 4096
Figure 4 Integral Non-Linearity
450000 400000 350000 Number of hits 300000 250000 200000 150000 100000 50000 0 808 809 80A A DC o u tp u t (He x) 80B 6498 56 113866 M ode 1 V INP = V INM =A V DD/2 No is e = 0.33 L SB r m s
399771
Figure 5 Shorted-Input Noise
w
PP Rev 1.2 August 2001 7
WM2152 DEVICE DESCRIPTION
INTRODUCTION
The WM2152 (see Block Digram on Page 1) consists of: * * * * * *
Product Preview
Programmable gain amplifier (PGA) including high bandwidth sample-and-hold. This is configured using control pins CON0, CON1. 12-bit, 30MSPS pipeline analog-to-digital converter (ADC) core On-chip generation of the ADC references VRT and VRB (or external references can be applied to these pins if EXTREF is set high) 12-bit parallel digital output, with separate supplies DVDD, DGND. Out-of-range output pin OVRNG goes high when the input signal exceeds the converter's range (positive or negative) The digital outputs, including OVRNG, are all set high-impedance if OEB is driven low.
CONFIGURATION DETAILS
The device is typically configured by tying pins CON0, CON1, and EXTREF high or low. * There are no pull-offs on these inputs, so they must not be left floating. * These inputs have protection diodes and input buffers connected to AVDD and AGND, so they should be tied to AVDD or AGND, not DVDD or DGND.
INTERNAL/EXTERNAL REFERENCES
Pin EXTREF controls whether the ADC voltage references are generated internally, or whether these are supplied externally (for applications where common or high precision references are required) EXTREF 0 1 Mode of Operation Internal References used External References applied.
INPUT SIGNAL RANGE/POWER-DOWN
Pins CON0, CON1 power down the chip, or configure the PGA as follows: MODE 0 1 2 3 CON1 0 0 1 1 CON0 0 1 0 1 Mode of Operation Device Powered Down Single Ended Mode / Differential Mode x1 Differential Mode x0.5 Single Ended Mode with Offset
Figure 6 illustrates the input signal ranges obtainable. (a) Mode1 - single-ended input: VINM is held constant, VINP acts as a single-ended input with zero-scale VINM-1V and full-scale VINM+1V. (Note VINP could be held constant and VINM used as the input with zero-scale VINP+1V, full-scale VINP-1V). (b) Mode 1 - differential: complementary inputs are applied to VINM and VINP. Zero scale when VINP-VINM=-1V, full-scale when VINP+VINM=+1V. (c) Mode 2 - differential mode x 0.5: as (b), but the PGA gain is reduced, so zero scale is now wVINP-VINM=-2V, full-scale when VINP+VINM=+2V. Mode 3 - single-ended with offset: In mode 3 an offset is applied within the PGA, so now zero scale is VINP=VINM, full-scale is when VINP=VIMN+1V. In this example, VINM is held constant and VINP swings 1V. This mode is useful for positive-going video signals, for example.
(d)
w
PP Rev 1.2 August 2001 8
WM2152
(e)
Product Preview
Mode 3 - single-ended with offset: as (d), but now VINP is held constant, and VINM is a negative going signal with respect to VINP.
Note: (i) (ii) In all cases, the effective input signal is VINP - VINM. The input has excellent common-mode rejection, so VINM and VINP may be placed anywhere between AVDD1 and AGND1. The above full-scale ranges assume the nominal internally generated ADC reference voltages, i.e. VRT-VRB = 1V. If externally applied references are used, and VRT-VRB is not 1V, the full-scale ranges will scale accordingly. E.g. in case (a) above, if VRT-VRB is 0.8V, zero scale will occur at VINP=VINM-0.8V, full scale at VINP=VINM+0.8V.
(iii)
4095 Output Code VINM
1V
4095
Output Code
1V
1V
NP VI
NM VI
VI NP
1V
Input voltages
(a) MODE 1, CON[1:0] = 01
4095
Output Code
VI NM
2V
NP VI
Input voltages
(c) MODE2, CON[1:0] = 10
4095 Output Code VINM 1V
VI NP
4095 Output Code
Input voltages
Input voltages
(d) MODE3, CON[1:0] = 11
(e) MODE3, CON[1:0] = 11
Figure 6 Input voltage ranges
w
VINP
0 0
0 0 0
Input voltages
(b) MODE 1, CON[1:0] = 01
1V
NM VI
PP Rev 1.2 August 2001 9
WM2152 APPLICATIONS INFORMATION
RECOMMENDED EXTERNAL COMPONENTS
DVDD 20 AVDD C1 C2 C3 DGND VRT AGND VRB 5 6 VINP VINM 9 10 C4 C5 27 AVDD2 8 AVDD1 AGND1 AGND2 7 1 AGND DGND DVDD DGND 19
Product Preview
Analog input signal
C7
C6
OVRNG
11 12 13 14 15 16 17 18 21 22 23 24 25
AGND
WM2152
Clock
28 CLK
D11 D10 D9 D8 D7 D6
DVDD + C8
AVDD + C9
2
D5 CON1 CON0 EXTREF D4 D3 D2 D1 OEB D0
Output Data Bus
DGND AGND
Mode Control Interface Control
3 4
26
NOTES: 1. C1-7 should be fitted as close to WM2152 as possible. 2. AGND and DGND should be connected as close to WM2152 as possible.
Figure 7 External Components Diagram COMPONENT REFERENCE C1 C2 C3 C4 C5 C6 C7 C8 C9 SUGGESTED VALUE 100nF 100nF 100nF 100nF 10F 100nF 100nF 10F 10F DESCRIPTION De-coupling for DVDD. De-coupling for AVDD2. De-coupling for AVDD1. High frequency de-coupling between VRT and VRB. Low frequency de-coupling between VRT and VRB (non-polarised). De-coupling for VRT. De-coupling for VRB. Reservoir capacitor for DVDD. Reservoir capacitor for AVDD.
Table 1 External Components Descriptions
w
PP Rev 1.2 August 2001 10
WM2152
USER TIPS FOR OBTAINING BEST PERFORMANCE FROM THE WM2152
* * *
Product Preview
Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short PCB traces.
Minimise capacitive loads on the digital outputs, to minimise on-chip current spikes. Use separately decoupled ground planes for digital and analog supplies and for AVDD1,AVDD2. and route any digital return currents away from sensitive analog nodes. * Keep all decoupling capacitors as close as possible to the respective supply or reference pins. * Solder the device directly to the PCB: socketing the device will introduce extra parasitic inductance and degrade decoupling * Small series resistors and shunt capacitors on the analog inputs will help pre-filter highfrequency noise and prevent it being aliased down by the sample-hold. These may also help the preceding amplifier to drive into the switched-capacitior inputs of the WM2152. An Evaluation Kit WM2152-EV1B is available for this part, consisting of an evaluation board and manual.
w
PP Rev 1.2 August 2001 11
WM2152
PACKAGE DIMENSIONS
DT: 28 PIN TSSOP (9.7 x 4.4 x 1.0 mm)
Product Preview
DM022.A
b
28
e
15
E1
E
GAUGE PLANE 1 14
D 0.25 c A A2 A1 -C0.1 C
SEATING PLANE
L
Symbols A A1 A2 b c D e E E1 L REF: MIN ----0.05 0.80 0.19 0.09 9.60
4.30 0.45 o 0
Dimensions (mm) NOM --------1.00 --------9.70 0.65 BSC 6.4 BSC 4.40 0.60 ----JEDEC.95, MO-153
MAX 1.20 0.15 1.05 0.30 0.20 9.80
4.50 0.75 o 8
NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE. C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.25MM. D. MEETS JEDEC.95 MO-153, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
w
PP Rev 1.2 August 2001 12
WM2152 IMPORTANT NOTICE
Product Preview
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QW United Kingdom
Tel :: +44 (0)131 667 9386 Fax :: +44 (0)131 667 5176 Email :: sales@wolfsonmicro.com
w
PP Rev 1.2 August 2001 13

▲Up To Search▲

Price & Availability of WM2152

	To Download WM2152 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .